Memory Administration Unit
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작성자 Celeste 작성일25-12-24 21:24 조회24회 댓글0건관련링크
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In trendy techniques, applications typically have addresses that entry the theoretical most memory of the pc architecture, 32 or 64 bits. The MMU maps the addresses from every program into separate areas in physical memory, which is usually a lot smaller than the theoretical most. This is possible because packages not often use giant amounts of memory at anyone time. Most modern working techniques (OS) work in live performance with an MMU to provide digital memory (VM) help. The MMU tracks memory use in fastened-dimension blocks often called pages. If a program refers to a location in a web page that's not in physical memory, the MMU sends an interrupt to the operating system. The OS selects a lesser-used block in memory, writes it to backing storage akin to a tough drive if it has been modified since it was learn in, reads the web page from backing storage into that block, and sets up the MMU to map the block to the originally requested page so this system can use it.
This is named demand paging. Some less complicated actual-time operating systems don't assist digital Memory Wave Program and don't need an MMU, however nonetheless want a hardware memory safety unit. MMUs generally provide memory safety to block makes an attempt by a program to access memory it has not previously requested, which prevents a misbehaving program from using up all memory or malicious code from reading information from another program. Zilog Z8000 family of processors. Later microprocessors (such because the Motorola 68030 and the Zilog Z280) positioned the MMU along with the CPU on the same built-in circuit, as did the Intel 80286 and later x86 microprocessors. Some early methods, especially 8-bit methods, used very simple MMUs to carry out financial institution switching. Early programs used base and bounds addressing that additional developed into segmentation, or used a fixed set of blocks instead of loading them on demand. The difference between these two approaches is the dimensions of the contiguous block of memory; paged systems break up main memory into a sequence of equal sized blocks, whereas segmented systems typically permit for variable sizes.
In segmented translation, a memory handle incorporates a segment quantity and an offset within the section. Segments are variable-size, and will have permissions, corresponding to read, write, and execute, related to them. A segment is loaded into a contiguous space of physical memory. Usually, the phase number is used as an index into a phase desk; every entry in the section desk holds the deal with of the area of bodily memory, the size of the section, and different data similar to permission flags. This type has the benefit of simplicity; the memory blocks are steady and thus only the two values, base and restrict, have to be stored for mapping purposes. The drawback of this method is that it leads to an effect referred to as external fragmentation. This happens when memory allocations are released but are non-contiguous. In this case, enough memory may be accessible to handle a request, but this is unfold out and can't be allocated to a single segment.
On programs where programs start and stop over time, this could ultimately lead to memory being highly fragmented and no giant blocks remaining; on this case, segments would need to be moved in memory, and their segment table entries modified to reflect the new bodily handle, Memory Wave Program to make a contiguous space giant enough for a section available. Some models of the PDP-11 16-bit minicomputer have a segmented memory administration unit with a set of page tackle registers (PARs) and page description registers (PDRs); this maps an 16-bit virtual deal with to an 18-bit physical tackle. The PDP-11/70 expands that to produce a 22-bit bodily address. Zilog Z8010, but many other examples exist. The Intel 8086, Intel 8088, Intel 80186, and Intel 80188 provide crude memory segmentation and no memory safety. The 16-bit section registers enable for 65,536 segments; each phase begins at a set offset equal to sixteen times the segment quantity; the segment beginning tackle granularity is sixteen bytes.
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