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DIMMs based mostly on Single Data Rate (SDR) DRAM have the identical bus frequency for data, free slots handle and management traces. The Pc/104 bus, used in industrial and embedded purposes, is a derivative of the ISA bus, utilizing the same signal strains with completely different connectors. In the case of "×4" registered DIMMs, the information width per facet is 36 bits; due to this fact, online Slots the reminiscence controller (which requires 72 bits) wants to handle each sides at the same time to read or write the data it needs.

Of the ranks that share the identical memory slot, i.e. on the identical module, only one rank may be accessed at any given time. For "×8" registered DIMMs, each facet is 72 bits extensive, so the memory controller solely addresses one aspect at a time (the two-sided module is twin-ranked).

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